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rev: 1.0 3 2 / 2000 1/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 64k x 32 2m synchronous burst sram 1 5 0mhz - 66 mhz 9 ns - 18 ns 3.3v vdd 3.3v & 2.5v i/o tqfp, qfp commercial temp industrial temp features ? ft pin for user configurable flow through or pipelined operation. ? single cycle deselect (scd) operation. ? high output drive current. ? 3.3v +10%/-5% core power supply ? 2.5v or 3.3v i/o supply. ? lbo pin for linear or interleaved burst mode. ? internal input resistors on mode pins allow floating mode pins. ? default to interleaved pipelined mode. ? byte write ( bw ) and/or global write ( gw ) operation. ? common data inputs and data outputs. ? clock control, registered, address, data, and control. ? internal self-timed write cycle. ? automatic power-down for portable applications. ? jedec standard 100-lead tqfp or qfp package. functional description applications the gs820 h 32 is a 2,097,152 bit high performance synchronous sram with a 2 bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpu?s, the device now finds application in synchronous sram applications ranging from dsp main store to networking chip set support. controls addresses, data i/o?s, chip enables ( e 1 , e 2 , e 3 ), a ddress burst control inputs ( adsp , adsc , adv ) and write control inputs ( bx , bw , gw ) are synchronous and are controlled by a positive edge triggered clock input (ck). output enable ( g ) and power down control (zz) are asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order ( lbo ) input. the burst function need not be used. new addresses can be loaded on every cycle with no degradation of chip performance. flow through / pipeline reads the function of the data output register can be controlled by the user via the ft mode pin/bump (pin 14 in the tqfp, bump 1f in the fp- bga). holding the ft mode pin /bump low , places the ram in flow through mode, causing output data to bypass the data output register. holding ft high places the ram in pipelined mode, activating the rising edge triggered data output register. pipelined reads the gs820 h 32 is a n scd (single cycle deselect) pipelined synchronous sram. dcd (dual cycle deselect) versions are also available. scd srams pipeline deselect commands one stage less than read commands. scd rams begin turning off their outputs immediately after the deselect command has been captured in the input registers. byte write and global write byte write operation is performed by using byte write enable ( bw ) input combined with one or more individual byte write signals ( bx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs820 h 32 operates on a 3.3v power supply and all inputs/ outputs are 3.3v and 2.5v compatible. separate output power ( v ddq ) pins are used to de-couple output noise from the internal circuit. -150 -138 -133 -117 -100 -66 pipeline 3-1-1-1 tcycle t kq i dd 6.6ns 3.8ns 270ma 7.25ns 4ns 245ma 7.5ns 4ns 240ma 8.5ns 4.5 210ma 10ns 5ns 180ma 12.5ns 6ns 150ma flow through 2-1-1-1 tcycle t kq i dd 10.5ns 9ns 170ma 15ns 9.7ns 120ma 15ns 10ns 120ma 15ns 11ns 120ma 15ns 12ns 120ma 20ns 18ns 95ma
rev: 1.0 3 2 / 2000 2/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 gs820 h 32 100 pin tqfp and qfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 ft v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq l b o a 5 a 4 a 3 a 2 a 1 a 0 n c n c v s s v d d n c n c a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 n c a 6 a 7 e 1 e 2 b d b c b b b a e 3 c k g w b w v d d v s s g a d s c a d s p a d v a 8 a 9 a 1 5 64k x 32 top view dq b5 nc dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 nc dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 nc dq c5 nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
rev: 1.0 3 2 / 2000 3/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 tqfp pin description h pin location symbol type description 37, 36 a 0 , a 1 i address field lsb?s and address counter preset inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49 a 2 - 15 i address inputs 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 dq a1 -dq a8 dq b1 -dq b8 dq c1 -dq c8 dq d1 -dq d8 i/o data input and output pins. 16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30 nc no connect 87 bw i byte write. writes all enabled bytes. active low. 93, 94 b a , b b i byte write enable for dq a , dq b data i/o?s. active low. 95, 96 b c , b d i byte write enable for dq c , dq d data i/o?s. active low. 89 ck i clock input signal. active high. 88 gw i global write enable. writes all bytes. active low. 98, 92 e 1 , e 3 i chip enable. active low. 97 e 2 i chip enable. active high. 86 g i output enable. active low. 83 adv i burst address counter advance enable. active low. 84, 85 adsp , adsc i address strobe (processor, cache controller). active low. 64 zz i sleep mode control. active high. 14 ft i flow through or pipeline mode. active low. 31 lbo i linear burst order mode. active low. 15, 41, 65, 91 v dd i core power supply. 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss i i/o and core ground. 4, 11, 20, 27, 54, 61, 70, 77 v ddq i output driver power supply.
rev: 1.0 3 2 / 2000 4/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 gs820 h 18/32/36 block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load d q d q register register d q register d q register d q register d q register d q register d q register d q r e g i s t e r d q r e g i s t e r a0-an lbo adv ck adsc adsp gw bw b a b b b c b d e 1 ft g zz power down control memory array 32 32 4 a q d e 2 e 3 dqx1-dqx8 1
rev: 1.0 3 2 / 2000 5/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 note: there are pull up devices on lbo and ft pins and a pull down device on and zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences byte write truth table note: 1. all byte outputs are active in read cycles regardless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/o?s remain high-z during all write operations regardless of the state of byte write enable inputs. mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb function gw bw b a b b b c b d notes read h h x x x x 1 read h l h h h h 1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all bytes h l l l l l 2, 3, 4 write all bytes l x x x x x linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.0 3 2 / 2000 6/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d note: 1. x = don?t care, h = high, l = low. 2. e = t (true) if e 2 = 1 and e 3 = 0; e = f (false) if e 2 = 0 or e 3 = 1. 3. w = t (true) and f (false) is defined in the byte write truth table preceding. 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. input combinations shown in gray boxes need not be used to accompli sh basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
rev: 1.0 3 2 / 2000 7/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 first write first read burst write burst read deselect r w cr cw x x w r r w r x x x s i m p l e s y n c h r o n o u s o p e r a t i o n s i m p l e b u r s t s y n c h r o n o u s o p e r a t i o n cr r cw cr cr simplified state diagram notes: 1. the diagram shows only supported (tested) synchronous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assumes active use of only the enable ( e 1, e 2, e 3 ) and write ( b a , b b , b c , b d , bw and gw ) control inputs and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together assume active use of only the enable, write and adsc control inputs and assumes adsp is tied high and adv is tied low.
rev: 1.0 3 2 / 2000 8/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 first write first read burst write burst read deselect r w cr cw x x w r r w r x x x cr r cw cr cr w cw w cw simplified state diagram with g notes: 1. the diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in grey tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
rev: 1.0 3 2 / 2000 9/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomme nded operating conditions. exposure to conditions exceeding the absolute maximum ratings, for an extended period of time, may affect reliability of this component. note: 1. unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75v vddq 2.375v (i.e. 2.5v i/o) and 3.6v vddq 3.135v (i.e. 3.3v i/o) and quoted at whichever condition is worst case. 2. this device features input buffers compatible with both 3.3v and 2.5v i/o drivers. 3. most speed grades and configurations of this device are of f ered in both commercial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be -2v > vi < v dd +2v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins -0.5 to 4.6 v v ddq voltage in v ddq pins -0.5 to v dd v v ck voltage on clock input pin -0.5 to 6 v v i/o voltage on i/o pins -0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins -0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/- 20 ma i out output current on any i/o pin +/- 20 ma p d package power dissipation 1.5 w t stg storage temperature -55 to 125 o c t bias temperature under bias -55 to 125 o c recommended operating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 v dd v 1 input high voltage v ih 1.7 --- v dd +0.3 v 2 input low voltage v il -0.3 --- 0.8 v 2 ambient temperature (commercial range versions) t a 0 25 70 c 3 ambient temperature (industrial range versions) t a -40 25 85 c 3
rev: 1.0 3 2 / 2000 10/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 note: this parameter is sample tested. notes: 1. junction temperature is a function of sram power dissipation, package thermal resistance, mounting board temperature, ambient. t emper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87. 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1. 4. for x18 configuration, consult factory. capacitance (t a =25 o c , f =1mh z , v dd =3.3v) parameter symbol test conditions typ. max. unit control input capacitance c i v dd =3.3v 3 4 pf input capacitance c in v in =0v 4 5 pf output capacitance c out v out =0v 6 7 pf package thermal characteristics rating layer board symbol tqfp max qfp max unit notes junction to ambient (at 200 lfm) single r q ja 40 tbd c/w 1,2,4 junction to ambient (at 200 lfm) four r q ja 24 tbd c/w 1,2,4 junction to case (top) r q jc 9 tbd c/w 3,4 20% tkc v ss -2.0v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd +-2.0v 50% v dd v il
rev: 1.0 3 2 / 2000 11/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz . 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3v input low level 0.2v input slew rate 1v/ns input reference level 1.25v output reference level 1.25v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd -1ua 1ua zz input current i in zz v dd 3 v in 3 v ih 0v v in v ih -1ua -1ua 1ua 300ua mode pin input current i in m v dd 3 v in 3 v il 0v v in v il -300ua -1ua 1ua 1ua output leakage current i ol output disable, v out = 0 to v dd -1ua 1ua output high voltage v oh i oh = - 8 ma, v ddq =2.375v 1.7v output high voltage v oh i oh = - 8 ma, v ddq =3.135v 2.4v output low voltage v ol i ol = 8 ma 0.4v dq vt=1.25v 50 w 30pf * dq 2.5v output load 1 output load 2 225 w 225 w 5pf * * distributed test jig capacitance
rev: 1.0 3 2 / 2000 12/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 operating currents operating currents parameter test conditions symbol -150 -138 -133 0 to 70c -40 to 85c 0 to 70c -40 to 85c 0 to 70c -40 to 85c operating current device selected; all other inputs 3 v ih o r v il output open i dd pipeline 270ma 275ma 245ma 250ma 240ma 245ma i dd flow-thru 170ma 175ma 120ma 125ma 120ma 125ma standby current zz 3 v dd - 0.2v i sb flow-thru 10ma 15ma 10ma 15ma 10ma 15ma deselect current device deselected; all other inputs 3 v ih or v il i dd pipeline 90ma 95ma 80ma 85ma 80ma 85ma i dd flow-thru 45ma 50ma 40ma 45ma 40ma 45ma parameter test conditions symbol -117 -100 -66 0 to 70c -40 to 85c 0 to 70c -40 to 85c 0 to 70c -40 to 85c operating current device selected; all other inputs 3 v ih o r v il output open i dd pipeline 210ma 215ma 180ma 185ma 150ma 155ma i dd flow-thru 120ma 125ma 120ma 125ma 95ma 100ma standby current zz 3 v dd - 0.2v i sb flow-thru 10ma 15ma 10ma 15ma 10ma 15ma deselect current device deselected; all other inputs 3 v ih or v il i dd pipeline 70ma 75ma 60ma 65ma 50ma 55ma i dd flow-thru 40ma 45ma 40ma 45ma 40ma 45ma
rev: 1.0 3 2 / 2000 13/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycle, zz must meet the specified setup and hold times as specified above. parameter symbol -150 -138 -133 -117 -100 -66 unit min max min max min max min max min max min max pipeline clock cycle time tkc 6.6 --- 7.25 --- 7.5 --- 8.5 --- 10 12.5 ns clock to output valid tkq --- 3.8 --- 4 --- 4 --- 4.5 5 6 ns clock to output invalid tkqx 1.5 --- 2 --- 2 --- 2 --- 2 2 ns clock to output in low-z tlz 1 1.5 --- 2 --- 2 --- 2 --- 2 2 ns flow- thru clock cycle time tkc 10.5 --- 15 --- 15 --- 15 --- 15 20 ns clock to output valid tkq --- 9.0 --- 9.7 --- 10 --- 11 12 18 ns clock to output invalid tkqx 3 --- 3 --- 3 --- 3 --- 3 3 ns clock to output in low-z tlz 1 3 --- 3 --- 3 --- 3 --- 3 3 ns clock high time tkh 1.8 --- 1.9 --- 1.9 --- 2 --- 3 4 ns clock low time tkl 1.8 --- 1.9 --- 1.9 --- 2 --- 3 4 ns clock to output in high-z thz 1 1.5 3.8 1.5 4 1.5 4 1.5 4 5 6 ns g to output valid toe --- 3.8 --- 4 --- 4 --- 4 5 6 ns g to output in low-z tolz 1 0 --- 0 --- 0 --- 0 --- 0 0 ns g to output in high-z tohz 1 --- 4 --- 4 --- 4 --- 4 5 6 ns setup time ts 1.7 --- 2 --- 2 --- 2 --- 2 2 ns hold time th 0.5 --- 0.5 --- 0.5 --- 0.5 --- 0.5 0.5 ns zz setup time tzzs 2 5 --- 5 --- 5 --- 5 --- 5 5 ns zz hold time tzzh 2 1 --- 1 --- 1 --- 1 --- 1 1 ns zz recovery tzzr 20 --- 20 --- 20 --- 20 --- 20 20 ns
rev: 1.0 3 2 / 2000 14/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 ck adsp adsc adv gw bw g wr2 wr3 wr1 wr1 wr2 wr3 tkc single write burst write d2 a d2 b d2 c d2 d d3 a d1 a t kl t kh ts th ts th ts th ts th ts th ts th ts th ts th write specified byte for 2 a and all bytes for 2 b , 2 c & 2 d adv must be inactive for adsp write adsc initiated write adsp is blocked by e 1 inactive a 0 -an b a - b d dq a - dq d write deselected hi-z wr1 wr2 wr3 write cycle timing e 1 e 3 ts th ts th ts th e 2 and e 3 only sampled with adsp or adsc e 1 masks adsp e 2 deselected with e 2
rev: 1.0 3 2 / 2000 15/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 q 1 a q 3 a q 2 d q 2 c q 2 b q 2 a tkq tlz toe tohz tolz tkqx thz tkqx ck adsp adsc bw g gw adv burst read rd2 rd3 tkl ts th th ts th ts th adsc initiated read suspend burst single read adsp is blocked by e 1 inactive a 0 -an b a - b d tkh tkc ts th ts ts th dq a -dq d rd1 hi-z suspend burst flow through read cycle timing e 2 ts th th th e 1 masks adsp e 2 and e 3 only sampled with adsp or adsc deselected with e 2 e 3 e 1 ts ts
rev: 1.0 3 2 / 2000 16/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 flow through read-write cycle timing ck adsp adsc adv gw bw g rd1 wr1 rd2 q1 a d1 a q2 a q2 b q2 c q2 d single read burst read toe tohz ts th ts th th ts th ts th ts th ts th tkh adsc initiated read dq a - dq d b a - b d a0-an tkl tkc ts single write adsp is blocked by e inactive tkq ts th hi-z q2 a burst wrap around to it?s initial state wr1 e 1 e 3 e 2 ts ts th ts e1 masks adsp e2 and e3 only sampled with adsp and adsc deselected with e3 th th
rev: 1.0 3 2 / 2000 17/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 pipelined scd read cycle timing q1 a q3 a q2 d q2 c q2 b q2 a tkq tlz toe tohz tolz tkqx thz tkqx ck adsp adsc bw g gw adv burst read rd2 rd3 tkl ts th th ts th ts th adsc initiated read suspend burst single read adsp is blocked by e 1 inactive a n bw a - bw d tkh tkc ts th ts ts th dq a - dq d rd1 hi-z e 2 ts th th th e1 masks adsp e 2 and e 3 only sampled with adsp or adsc deselected with e 2 e 3 e 1 ts ts
rev: 1.0 3 2 / 2000 18/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 ck adsp adv gw bw g q1 a d1 a q2 a q2 b q2 c q2 d single read burst read toe tohz ts th ts th th ts th ts th tkh dqa - dqd b a - bw d tkl tkc ts single write adsp is blocked by e inactive tkq ts th hi-z pipelined scd read - write cycle timing wr1 adsc ts th adsc initiated read rd1 wr1 rd2 ts th a 0 -an e 1 e 3 e 2 ts ts th ts e1 masks adsp e2 and e3 only sampled with adsp and adsc deselected with e3 th th
rev: 1.0 3 2 / 2000 19/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 application tips single and dual cycle deselect scd devices force the use of ?dummy read cycles? (read cycles that are launched normally but that are ended with the output driv ers inactive) in a fully synchronous environment. dummy read cycles waste performance but their use usually assures there will be no bus contenti on in transitions from reads to writes or between banks of rams. dcd srams do not waste bandwidth on dummy cycles and are logically s impler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care mus t be exercised to avoid excessive bus contention. gs 820 h 32 output driver characteristics ck adsp adsc th tkh tkl tkc ts zz tzzr tzzh tzzs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ snooze sleep mode timing diagram
rev: 1.0 3 2 / 2000 20/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 h -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 v out (pull down) vddq - v out (pull up) i out (ma) 3.6v pd hd 3.3v pd hd 3.1v pd hd 3.1v pu hd 3.3v pu hd 3.6v pu hd pull up drivers pull down drivers vddq vout i out vss
rev: 1.0 3 2 / 2000 21/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 tqfpand qfp package drawing d 1 d e1 e p i n 1 b e c l l1 a2 a1 y q notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion tqfp qfp symbol description min. nom. max min. nom. max a1 standoff 0.05 0.10 0.15 0.25 0.35 0.45 a2 body thickness 1.35 1.40 1.45 2.55 2.72 2.90 b lead width 0.20 0.30 0.40 0.20 0.30 0.40 c lead thickness 0.09 0.20 0.10 0.15 0.20 d terminal dimension 21.9 22.0 22.1 22.95 23.2 23.45 d1 package body 19.9 20.0 20.1 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 17.0 17.2 17.4 e1 package body 13.9 14.0 14.1 13.9 14.0 14.1 e lead pitch 0.65 0.65 l foot length 0.45 0.60 0.75 .60 0.80 1.00 l1 lead length 1.00 1.60 y coplanarity 0.10 0.10 q lead angle 0 7 0 7
rev: 1.0 3 2 / 2000 22/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 org part number 1 type package speed 2 (mhz/ ns) t a 3 status 64k x 32 gs820 h 32 t-150 pipeline/flow through tqfp 150/9 c 64k x 32 gs820 h 32 t-138 pipeline/flow through tqfp 138/9.7 c 64k x 32 gs820 h 32 t-133 pipeline/flow through tqfp 133/10 c 64k x 32 gs820 h 32 t -4 pipeline/flow through tqfp 117/11 c 64k x 32 gs820 h 32 t -5 pipeline/flow through tqfp 100/12 c 64k x 32 gs820 h 32 t -6 pipeline/flow through tqfp 66/18 c 64k x 32 gs820 h 32 t-150i pipeline/flow through tqfp 150/9 i not available 64k x 32 gs820 h 32 t-138i pipeline/flow through tqfp 138/9.7 i 64k x 32 gs820 h 32 t-133i pipeline/flow through tqfp 133/10 i 64k x 32 gs820 h 32 t -4 i pipeline/flow through tqfp 117/11 i 64k x 32 gs820 h 32 t -5 i pipeline/flow through tqfp 100/12 i 64k x 32 gs820 h 32 t -6 i pipeline/flow through tqfp 66/18 i 64k x 32 gs820 h 32 q-150 pipeline/flow through qfp 150/9 c 64k x 32 gs820 h 32 q-138 pipeline/flow through qfp 138/9.7 c 64k x 32 gs820 h 32 q-133 pipeline/flow through qfp 133/10 c 64k x 32 gs820 h 32 q -4 pipeline/flow through qfp 117/11 c 64k x 32 gs820 h 32 q -5 pipeline/flow through qfp 100/12 c 64k x 32 gs820 h 32 q -6 pipeline/flow through qfp 66/18 c 64k x 32 gs820 h 32 q-150i pipeline/flow through qfp 150/9 i not available 64k x 32 gs820 h 32 q-138i pipeline/flow through qfp 138/9.7 i 64k x 32 gs820 h 32 q-133i pipeline/flow through qfp 133/10 i 64k x 32 gs820 h 32 q -4 i pipeline/flow through qfp 117/11 i 64k x 32 gs820 h 32 q -5 i pipeline/flow through qfp 100/12 i 64k x 32 gs820 h 32 q -6 i pipeline/flow through qfp 66/18 i notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs820 h 32t-100it. 2. the speed column indicates the cycle frequency (mhz) of the device in pipelined mode and the latency (ns) in flow through mode. each device is pipeline / flow through mode selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. see the gsi technology web site for a complete listing of current offerings.
rev: 1.0 3 2 / 2000 23/23 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. d gs820 h 32t/q -150/138/133/117/100/66 revision history ds/daterev. code: old; new types of changes format or content revisions gs gs820 h 32 18/36 rev 1.00 9/1999a format ? this was the first release of 2 meg burst datasheets in the new format. they included information for the fine pitch bga package. gs gs820 h 32 18/36 rev 1.00 9/1999a; 1.01 11/1999b content ? took out the fine pitch bga information. gs gs820 h 32 18/36 rev 1.01 11/1999b; 1.02 1/2000c content ? ordering information. changed 128k x 32 to 64k x 32; typo ? ordering information. changed ?0? to go before ?h? or ?e? in part number. ? ordering information. changed - 117 to -4, -100 to -5. and -66 to -6. gs820 h 32 18/36 1.02 1/ 2000c;820 h 32 18/36 1.03 2/ 2000d format/content ? new gsi logo ? switched tkq with tcycle in flow through part of table on page 1.

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